Standby power consumption is one of the main points of competition of mobile terminal products. The standby power consumption depends on a lot of factors, the most critical one of which is dynamic power consumption generated when receiving paging after waking up in a standby process. Main factors affecting wakeup time include warm-up, synchronization, receiving and demodulation, measurement, and low frequency clock calibration. In most solutions, the clock calibration is the most time-consuming factor, and thus becomes one of the major factors affecting the standby power consumption.
Generally, a high frequency clock source of a system is a 26 megahertz (MHz) voltage-controlled temperature compensated crystal oscillator (VCTCXO). This VCTCXO is frequency doubled to a 52 MHz (or other frequencies) high frequency clock source by a phase-lock loop (PLL) inside a wireless baseband chip, and is then used as a system clock. Because the VCTCXO needs to consume 2 milliamps (mA) to 4 mA power, power consumption is high. To reduce the power consumption, a low frequency clock output by a 32.768 K crystal oscillator is generally used in a sleep state of the system to maintain system timing, and this low frequency clock is also called a sleep clock.
Specifically, in a standby mode, a terminal implements a sleep-wakeup process according to a discontinuous reception (DRX) period configured by a network side, the high frequency clock is stopped at the time of sleep to reduce power consumption, and the low frequency clock is used to produce various needed time sequences and perform timing. However, both the high frequency clock and the low frequency clock have frequency deviations due to physical characteristics of the clock. The frequency deviation of the high frequency clock is kept within the range of 0.1 parts per million (ppm) through an automatic frequency calibration. The low frequency clock has poor frequency stability because it is generated by the crystal oscillator, and the frequency deviation generally ranges from 30 ppm to 50 ppm in the total temperature range.
Therefore, at the beginning of each DRX period, the low frequency clock needs to be calibrated first, and the number of sleep cycles of the low frequency clock is calculated and obtained when the terminal is in the sleep state. In this way, the terminal may execute the sleep-wakeup process after the low frequency clock experiences several sleep cycles, and perform signal reception at the network side. The terminal can enter a real sleep state only after the number of sleep cycles is calculated and obtained. Therefore, through the foregoing low frequency clock calibration, failure of reception of network signals by the terminal is prevented when the frequency deviation of the low frequency clock exceeds a maximum frequency deviation allowed by the system. In the prior art, an implementation method for calibrating a low frequency clock is generally: determining the number M of high frequency clock cycles corresponding to preset N low frequency clock cycles; calculating a ratio of N to M and obtaining a frequency of a low frequency clock; calculating the number of sleep cycles according to the frequency of the low frequency clock, and calibrating the low frequency clock. The system can enter the real sleep state only after the calibration is completed.
In the foregoing clock calibration method, in the case that the clock stability has no error, an error of 0 to 2 high frequency clock cycles may still occur in a calibration process because the low frequency clock is not synchronized with the high frequency clock. As shown in FIG. 1, an error may occur in a calibration process according to the foregoing figure. To reduce the impact of the error in the prior art, calibration time needs to be prolonged, that is, the real sleep time of the system needs to be reduced and thus the power consumption of the system is increased. In addition, the calibration method cannot predict the frequency deviation of the low frequency clock, where the frequency deviation of the low frequency clock is caused by temperature change when the terminal enters the sleep state after the calibration is completed. For example, if the temperature changes greatly, the frequency deviation of the low frequency clock may exceed the maximum frequency deviation allowed by the system when the terminal enters the sleep state after the clock is calibrated, which may still cause failure of reception of network signals by the terminal.